DIVIDER: This fine
line between the CPU
cores is actually made of
Philadelphia-brand cream
cheese. OK, it’s not,
but the cores cannot
communicate with each
other across this barrier;
they can only talk via the
front-side bus.BRANCH PREDICTION UNIT: The 90nm
Prescott core features an extremely long 32-
stage instruction pipeline. Like a factory assem-
bly line with 32 people performing only one task
each, data moves down the line much faster
than it would in a factory with 10 people per-
forming three tasks each. The problem with this
long pipeline is that if something goes wrong,
you’re forced to clear the entire assembly line
and toss out all the work in progress. A 10-stage
pipeline can get back up and running much
faster than a 32-stage pipeline. In the Pentium
D, the branch prediction unit has been further
refined in order to hold branch mispredictions to
a minimum, so the processor is always working
at peak efficiency.TRACE CACHE: The
ancient x86 architecture has
survived the onslaught of
RISC processors by adopting
reduced instruction set-like
abilities. Today’s x86 CISC
(complex instruction-set
CPUs) are amazingly RISC-
like in the way they break
complex instructions into
simple instructions. Intel’s
P4 and its dual-core deriva-
tives use trace cache to buf-
fer decoded instructions.16K DATA CACHE: As does the
90nm Prescott Pentium 4, the PD
features L1 data cache that’s double
the size of the original Willamette
Pentium 4. Just as L2 is several
magnitudes faster than main system
RAM, L1 cache is several magni-
tudes faster than L2 cache.L2 CACHE: Level 2 cache has
been integrated into CPU cores
as early as the AMD K6-III,
which had 256KB of cache.
Today, the Pentium D features
two separate 1MB L2 caches to
keep both engines well stoked
with data. Generally speaking,
more cache (which delivers data
several orders of magnitude
faster than main memory) helps
boost processor speeds by
caching the data that the actual
execution units munch on.ALU AND REGISTERS: The
arithmetic and logic unit handles
most of the basic math, such
as addition and subtraction. This
section also includes the register,
which is used to temporarily hold
values such as addresses.FLOATING-POINT UNIT: Old-
timers will remember having to pay
extra to get a “math co-processor;”
today, FPUs are built into the cores.
Each separate core in the Pentium
D features its own FPU, and each
FPU is slightly improved from the
Northwood version.Dual Core Dissected
Take a close look at what’s under the Pentium D’s heat spreader.
Here you can see the CPU’s paired cores and the line that
divides them.
JUNE 2005 MA XIMUMPC
CORE #1
CORE # 2