MaximumPC 2005 06

Dual Processor vs. Dual Core

On the surface, it might seem like dual-core processors and dual-processor systems are

roughly the same thing, but the respective architectures are actually quite different. Here’s

a look at how AMD’s and Intel’s dual-proc and dual-core architectures stack up

INTEL XEON: Intel’s dual-processor architecture is often
criticized for its reliance on a single front-side bus: In this example,
the two CPUs are connected by a single front-side bus running at
800MHz. Despite criticism that the shared bus is inferior to point-to-
point designs, Intel has propped up the performance of its dual pro-
cessors by increasing cache size and front-side bus speed. But what
happens when you drop in two dual-core processors? Will four cores
vying for access to main memory and the chipset turn the 800MHz
front-side bus into a traffic jam along the lines of downtown Manhat-
tan, or will Intel prove the naysayers wrong? We don’t know, but with
Intel’s plans to add a second front-side bus to its chipset for quad
Xeon machines, it’s possible that the shared-bus design is coming to
an end. Is an integrated memory controller on the way?

INTEL PENTIUM D: Intel’s Pentium

D might yield amazingly similar performance to a

dual-processor Xeon clocked at the same speed.

Both technologies share a single 800MHz front-side

bus and similar cores. One advantage the Pentium

D will have over the Xeon is the ability to run unbuf-

fered or nonregistered memory. Still, overall per-

formance of the PD and PEE should be remarkably

similar to dual Xeons. The pricey Xeons, however,

will probably stay ahead of the power curve with

fatter L3 cache to compensate for memory-band-

width issues.

CHIPSET RAM CHIPSET RAM

CPU 1 CPU 2 Core 1 Core 2

RAM

CPU 1

AMD OPTERON: AMD designed the Opteron
with multi-processor support in mind. Each processor can
address its own independent bank of RAM using its on-die
memory controller, and both procs can be connected to
the chipset and other CPUs through dedicated high-speed
HyperTransport links. With dual cores dropped in the
sockets, AMD’s architecture looks to be the most efficient,
because two cores only have to share one bank of memory
and they don’t have to rely on the front-side bus to talk.

AMD ATHLON 64 X2: One limitation that

Athlon 64 X2s must contend with is their shared memory

controller. Although each CPU core is a separate entity, they

share a single memory controller, and this could potentially

hurt performance (at least when compared with a dual-pro-

cessor Opteron). AMD claims this is all just hooey spread by

its competitors. The company says the criticism is especially

unfair because the Pentium D uses a shared bus and a shared

memory controller, while AMD’s CPU cores can communicate

via the crossbar. The proof will be in the pudding when X2s

hit the street this summer.

CPU 2 RAM CHIPSET

RAM

CHIPSET

Core 1

Core 2

JUNE 2005 MA XIMUMPC 49