quickstart THE BEGINNING OF THE MAGAZINE, WHERE ARTICLES ARE SMALL
S
hakespeare himself could have
penned the tragic rise and fall of the
mighty Pentium 4 processor. In 2000 A.D.,
with war brewing between Intel and the
neighboring kingdom of Athlon, the weak-
ening Pentium III was dethroned by the
upstart Pentium 4 and its promise of multi-
gigahertz computing. But the Pentium III
would have its revenge in the form of its
heir: The power-sipping Pentium M core
(also known as Banias). Now, five years
after the death of the PIII, the reign of the
Pentium 4 is coming to an end; Intel has
finally outlined broad plans to replace the
P4’s NetBurst architecture with one far
closer to that of the Pentium M.
This “next-generation” micro-architec-
ture will use the CPU code-named Conroe,
and will eschew the ultra-high clock speeds
(and corresponding excessive heat and
power requirements) of the Pentium 4 for a
rubric Intel calls “performance per watt.”SO LONG,
NETBURST
Does this mean Intel’s
NetBurst architecture is
singing its swan song?
Intel officials hemmed
and hawed when we
asked, but experts
were more forthcoming.
“NetBurst is dead,” said
Kevin Krewell, editor of
Microprocessor Report. Krewell said there
are certainly processors based on NetBurst
coming down the pike, but the architecture
is clearly going away. Furthermore, technol-
ogy achievements, such as the much-touted
trace cache, won’t be in the Conroe, Krewell
said. “Intel just doesn’t want to admit it spent
all this time and effort on a micro-architecture
that went nowhere.”
When released in late 2006, Conroe
should slot into LGA775 motherboards
and might even work with some of today’s
mobos. Beneath the heat spreader, how-ever, the new chip will be quite different
from today’s Socket 775 procs. While the
Pentium 4 features a 31-stage instruction
pipeline and runs up to 3.8GHz, the Conroe
will feature a 14-stage pipeline and will likely
run around 2GHz.
The dual cores in the first Conroe
CPUs will also feature a new ability: Their
L1 cache will directly communicate, so if
one core needs something that’s already in
the other core’s L1 cache, it can just grab
it directly from cache, instead of accessing
it across the much slower front-side bus.
Intel has also designed the next-gen core
with a high-performance engine that can
issue four instructions per clock cycle. At
its best, the Pentium 4 could issue three
instructions per clock and the Pentium M
could issue two.
All this, Intel says, amounts to a CPU
that should be up to five times faster than
the P4 in certain operations, while gen-
erating roughly half the heat. What will
happen to the P4? Once the multi-core
Conroe is introduced late next year, the
P4 will probably be rebadged as a Celeron
and spend the rest of its natural life toiling
away in the value-market Gulag.Goodbye,
Pentium 4
10 MA XIMUMPC NOVEMBER 2005
Intel moves to base all its processors on a new,
low-wattage micro-architecture that promises
a 5x performance increase over the P
The P4 Prescott’s 31-stage pipeline and NetBurst
architecture will always be remembered.PENTIUM III PENTIUM 4/D PENTIUM M NEXT-GEN CPUINTEL CPUs COMPARED
MICRO-ARCHITECTURE P6 Enhanced NetBurst Banias Not disclosed
PIPELINE STAGES 10 31 Not disclosed but believed 14
to be 14-
CLOCKS SPEEDS 450MHz – 1GHz 1.5GHz-3.8GHz 1.6GHz – 2.13GHz Not disclosed
(HIGHEST AT LAUNCH)
CORES 1 1 or 2 1 or 2 2 or more
FRONT-SIDE BUS 100MHz, 133MHz 400MHz, 533MHz, 400MHz, 533MHz Expected to be
800MHz, 1066MHz 800MHz to 1066MHz+
ADVANCED FEATURES SSE SSE, SSE2, SSE3, AMD64 SSE, SSE2, NX SSE, SSE2, SSE3, Dual
NX, Hyper-Threading, Core, Vanderpool
Dual Core Technology, Intel
Advanced Management
Technology, AMD^