MaximumPC 2007 07

T his ain’t your father’s Intel. The old Intel

would introduce a new microarchitecture

and milk it for almost a decade with the

most minute of tweaks every few years. When the

competition would start to breathe down its neck, Intel

fi xed the problem with marketing and, umm, higher

frequencies, more cache, and some new instructions.

This strategy ended with Intel crumpled on the fl oor

while AMD’s Athlon 64 pranced about like a happy,

happy pony.

Well, as they say, failure breeds victory, and

Intel has indeed emerged from its trouncing as a

leaner, meaner company. No longer building CPUs

just for the sake of maximizing profi ts, the com-

pany is pushing a new strategy that seems fi xed on

maximizing performance and pain to its competition.

This month we went to Intel’s headquarters for a

hands-on preview of the company’s follow-up to the

current prize-winning Core 2 chips, as well as a look at

what may very well be the Core 3.

pain to its competition.

This month we went to Intel’s headquarters for a

hands-on preview of the company’s follow-up to the

current prize-winning Core 2 chips, as well as a look at

what may very well be the Core 3.

I

ntel is a proud company, and

from what we can tell, it’s determined

to never have its ass handed to it again

by AMD, as happened when AMD released

its Athlon, Athlon XP, and Athlon 64 CPUs.

Following the Athlon 64 ass-whooping, Intel

adopted what it calls a “tick-tock” philoso-

phy—a tick amounts to a die shrink with

some feature enhancements, while a tock is

an entirely new microarchitecture.

For example, the fi rst tick was the

Presler Pentium D, which was mostly a core

shrink from the previous NetBurst chip. The

tock was the new Core microarchitecture

behind the champion Core 2 chips. Intel

plans to tick again late this year with the

Penryn CPU, which moves from a 65nm

to a 45nm process. Following that will be a

tock in 2008 with the new 45nm microarchi-

tecture code-named Nehalem.

The next tick will be a shrink to 32nm

in 2009 with an improved core called

Westmere. The tock will strike in 2010 with

the Gesher core, which will feature yet anoth-

er new microarchitecture. Get the picture?

This is a radical departure from the

Pentium 4/NetBurst microarchitecture,

which went from 180nm to 130nm,

and from 90nm to 65nm over almost

six years with very few changes. Why

such a brutal schedule? We believe Intel

is leveraging its ability to run multiple

design teams in parallel in the hopes

of wearing down AMD. It’s reminiscent

of the great graphics wars between ATI

and Nvidia, in which both companies

would hustle to release a brand-new

graphics core every 18 months.

PENRYN: UP CLOSE

AND PERSONAL

It may be designated as a tick, but Intel’s

Penryn is more than a mere die shrink.

Intel has made numerous improvements

to keep this CPU in the game. Many of

Penryn’s enhancements are aimed at

increasing performance in today’s applica-

tions, not those apps that won’t be out for

another three years—further proof that Intel

has no intention of standing still.

The Penryn’s design is similar to the

current Core 2 Duo and Core 2 Quad.

Natively, Penryn is a dual-core CPU; Intel

will create quad-core versions by joining

two CPUs via the front-side bus inside the

CPU heat spreader. To keep communication

between the two chips from bogging down,

Intel will up the FSB in all Penryns from

1,066MHz to 1,333MHz. Xeon versions

of the chip will also get a 1,600MHz FSB.

Penryn will feature 6MB of L2 in dual-core

chips and 12MB in quad cores, a 50 per-

cent increase over the current Core 2 chips.

Intel expects performance increases

with existing apps thanks to a new Fast

Radix-16 divider, which will, theoretically,

double division-math performance.

Media encoding, already something the

current Core 2 kicks butt at, will get a boost

through a “super shuffl e engine,” which will

optimize data housekeeping operations

used by SSE instructions. The super shuffl e

engine will let Penryn perform 128-bit

shuffl es in a single cycle, which will increase

performance on any SSE2 or SSE3 instruc-

tions without requiring any software rewrites

or even recompiles. Media encoding will

get a further boost when developers adopt

a new instruction set called SSE4. To the

folks who don’t take instruction sets seri-

ously, Intel says that SSE4 will dedicate cir-

cuits on the CPU to typical encoding tasks,

which should result in a huge performance

boost in apps that use the instructions.

One other feature Intel is building into

Penryn (and the upcoming mobile Centrino

Pro CPUs) is Dynamic Acceleration

Technology. Typically, in applications that

use only one core, the second core will

go into a low-power mode. With Penryn,

Intel plans to leverage the second core’s

decreased heat output by dynamically

cranking up the clocks on the fi rst core.

Intel plans to manufacture its next-gen

chips in volume later this year at clock

speeds greater than 3GHz and sell them by

early 2008, but there are indications that the

CPU behemoth could ship faster processors

earlier to pee on AMD’s quad-core parade,

which is scheduled for this summer.

DOC OCTOCORE: NEHALEM

REVEALED

Nehalem, the CPU coming after Penryn,

isn’t expected until next year, but the

“New Intel” is being a Chatty Cathy about

50 MAXIMUMPC july 2007

INTELSTRIKESBACK

his ain’t your father’s Intel. The old Intel

most minute of tweaks every few years. When the

his ain’t your father’s Intel. The old Intel

most minute of tweaks every few years. When the

Intel has indeed emerged from its trouncing as a

leaner, meaner company. No longer building CPUs

just for the sake of maximizing profi ts, the com-