CHAPTER 6. DEVELOPING ESSENTIAL DEVICE DRIVERS AND A
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Internally, controller chips usually have several registers that can be read, written or
both by the CPU, and it is the state of these registers that tell the controller what to
do (e.g. what pins to set high or low to drive the hardware, or what internal function to
perform). As an example, from the datasheet of Intel’s widely used82077AAsingle-chip
floppy disk controller [?], we see there is a pin (pin 57, labelledME0) that drives the motor
of the first floppy disk device (since a single controller can drive several such devices):
when the pin is on, the motor spins; when off, the motor does not spin. The state of
this particular pin is directly linked to a particular bit of the controller’s internal register
named the Digital Output Register (DOR). The state of that register can then be set by
setting a value, with the appropriate bit set (bit 4, in this case), across the chip’s data
pins, labelledDB0--DB7, and using the chip’s register selection pins,A0--A2, to select
theDORregister by its internal address0x2.
6.1.1 I/O Buses
Although historically the CPU would talk directly to device controllers, with ever in-
creasing CPU speeds, that would require the CPU artificially to slow down to the same
speed as the slowest device, so it is more practical for the CPU to issue I/O instructions
directly to the controller chip of a high-speed, top-levelbus. The bus controller is then
responsible for relaying, at a compatible rate, the instructions to a particular device’s
controller. Then to avoid the top-level bus having to slow down for slower devices, the
controller of a another bus technology may be added as a device, such that we arrive at
the hierarchy of buses found in modern computers [?].
6.1.2 I/O Programming
So the question is, how do we read and write the registers of our device controllers (i.e.
tell our devices what to do) programatically? In Intel architecture systems the registers
of device controllers are mapped into an I/O address space, that is seperate from the main
memory address space, then varients of the I/O instructionsinandoutare used to read
and write data to the I/O addresses that are mapped to specific controller registers. For
example, the floppy disk controller descibed earlier usually has itsDORregister mapped to
I/O address0x3F2, so we could switch on the motor of the first drive with the following
instructions:
mov dx, 0x3f2 ; Must use DX to store port address
in al , dx ; Read contents of port (i.e. DOR) to AL
or al , 00001000b ; Switch on the motor bit
out dx, al ; Update DOR of the device.In older systems, such as the Industry Standard Architecture (ISA) bus, the port ad-
dresses would be statically assigned to the devices, but with modern plug-and-play buses,
such as Peripheral Component Interconnect (PCI), BIOS can dynamically allocate I/O
address to most devices before booting the operating system. Such dynamic allocation
requires devices to communicate configuration information over the bus to describe the
hardware such as: how many I/O ports are required to be reserved for the registers; how
much memory-mapped space is required; and a unique ID of the hardware type, to allow
appropriate drivers to be found later by the operating system [?].