Bunnie Huang
COLUMN
SPARK
Bunnie Huang
Andrew ‘Bunnie’ Huang is a
hacker by night, entrepreneur
by day, and writer by
procrastination. He’s a
co‑founder of Chibitronics,
troublemaker‑at‑large for the
MIT Media Lab, and a mentor
for HAX in Shenzhen.
he vast majority of chips
today consist of a single
fleck of silicon, usually in
some sort of a package to
protect the chip and make it
easier to mount to a circuit
board. In the 1980s, silicon was wire
bonded into DIP lead frames; in the 1990s,
the industry transitioned to surface-mount
flat-packs and ball grid arrays; and in the
new millennium, chip-scale packages rose
to dominance. Regardless of how the chips
came, the rule was typically one chip per
package, with the main exceptions being
flash memory chips which could be easily
stacked using
conventional wire
bonding techniques,
and a few mobile
phone CPUs that
could afford
exotic processes.
This may soon no
longer be the rule. In
what appears to be a
hedge against the
end of Moore’s Law, foundries are investing
heavily in next-generation packaging
technology that allows a single ‘chip’ to
contain multiple silicon die. AMD’s Ryzen
‘chiplet’ architecture and graphics chips
using stacked HBM are just a hint of what’s
to come. TSMC recently revealed a buffet
of mouth-watering packaging options that
will blur the distinction between individual
silicon chips, and the package containing
them. Three major trends – through-
silicon vias, integrated fan-out, and chip-
on-wafer-on-substrate – are allowingdesigners to mix and match chips from
processes optimised for logic, RF, analogue,
and memory into a single, high-
performance package no larger than your
traditional single-chip package. The new
packaging technology is also disruptive
because it improves I/O density and on-
chip performance. Increased I/O density
means more I/O bandwidth, which is good
news for today’s memory bandwidth-
bound CPUs.
The on-chip performance advantage
isn’t quite as obvious, but the performance
of chips isn’t just constrained by how fast
transistors can switch on and off. It’s also
constrained by how
much power you can
get into and out of the
package. Desktop
CPUs can draw over
100 amperes of
current (the typical
wall outlet in your
house is limited to
about 10–20 amperes,
albeit at a much
higher voltage). At these phenomenal
ampacities, even tiny imperfections
introduced by the package will make the
CPU unstable. The latest round of
packaging technology promises to push up
the power ceiling by an amount that will
equate to at least one generation of Moore’s
Law improvement in performance.
The slowing of Moore’s Law may be bad
for increased transistor densities on a
single chip, but it also marks the beginning
of a new race to improve the incredible
shrinking chip package.The incredible shrinking
chip package
Squeezing more sand into your computers
T
AMD’s Ryzen ‘chiplet’
architecture and
graphics chips using
stacked HBM are just a
hint of what’s to come@bunniestudios