Assembly Language for Beginners

.2. ARM

.2.2 Versions.

• ARMv4: Thumb mode introduced.


• ARMv6: used in iPhone 1st gen., iPhone 3G (Samsung 32-bit RISC ARM 1176JZ(F)-S that supports
  Thumb-2)


• ARMv7: Thumb-2 was added (2003). was used in iPhone 3GS, iPhone 4, iPad 1st gen. (ARM Cortex-
  A8), iPad 2 (Cortex-A9), iPad 3rd gen.


• ARMv7s: New instructions added. Was used in iPhone 5, iPhone 5c, iPad 4th gen. (Apple A6).


• ARMv8: 64-bit CPU,AKAARM64AKAAArch64. Was used in iPhone 5S, iPad Air (Apple A7). There is
  no Thumb mode in 64-bit mode, only ARM (4-byte instructions).

.2.3 32-bit ARM (AArch32).

General purpose registers

• R0— function result is usually returned using R0


• R1...R12—GPRs


• R13—AKASP (stack pointer)


• R14—AKALR (link register)


• R15—AKAPC (program counter)

R0-R3 are also called “scratch registers”: the function’s arguments are usually passed in them, and the
values in them are not required to be restored upon the function’s exit.

Current Program Status Register (CPSR)

Bit Description

0..4 M—processor mode

5 T—Thumb state

6 F—FIQ disable

7 I—IRQ disable

8 A—imprecise data abort disable

9 E—data endianness

10..15, 25, 26 IT—if-then state

16..19 GE—greater-than-or-equal-to

20..23 DNM—do not modify

24 J—Java state

27 Q—sticky overflow

28 V—overflow

29 C—carry/borrow/extend

30 Z—zero bit

31 N—negative/less than

VFP (floating point) and NEON registers

0..31bits 32..64 65..96 97..127

Q0128 bits

D064 bits D1

S032 bits S1 S2 S3

S-registers are 32-bit, used for the storage of single precision numbers.

D-registers are 64-bit ones, used for the storage of double precision numbers.

D- and S-registers share the same physical space in the CPU—it is possible to access a D-register via the
S-registers (it is senseless though).