Nature - 2019.08.29

(Frankie) #1

reSeArcH Article


(1) RINSE (removal of incubated nanotubes through selective exfo-


liation). We propose a method of removing CNT aggregate defects
through a selective mechanical exfoliation process. RINSE reduces CNT


aggregate defect density by > 250 × without affecting non-aggregated
CNTs or degrading CNFET performance.


(2) MIXED (metal interface engineering crossed with electrostatic
doping). Our combined CNT doping process leverages both metal con-
tact work function engineering as well as electrostatic doping to realize
a robust wafer-scale CNFET CMOS process. We experimentally yield
entire dies with >10,000 CNFET CMOS digital logic gates (2-input

SourceDrain

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eeecceeeeeeeceeeeececeeeeeeeceeeeeeeeeeeceeceeeeeeeeeeceeceeeeeeeeeeceeeceeceeeeeeeeceeceeeeceeeeceeeeeeeceeeceeeeeceeeeeeecececeeeeeeeeeeeeeeeeeeeeeececccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
crccccccccccccccccccrcrcccccccrcrcrcrccrcrcrcrcrcrcr
DraDDDDDD

innni

~7 mm

~7 mm Metal layer 1
(signal routing)

Metal layer 2
(CNFET gate +
signal routing)

Metal layer 3
(p-CNFET S/D +
intercell routing)

Metal layer 4
(n-CNFET S/D)

Metal layer 5
(power distribution)

Metal via

Metal via

Metal via

CNT

CNFETs

C

100 μm 40 μm 20 μm 1 μm

CNTs
2

ab

Fig. 1 | RV16X-NANO. a, Image of a fabricated RV16X-NANO chip. The
die area is 6.912 mm × 6.912 mm, with input/output pads placed around
the periphery. Scanning electron microscopy images with increasing
magnification are shown below (one image is false-coloured to match the
colouring in the schematic in b). RV16X-NANO is fabricated entirely from
CNFET CMOS, in a wafer-scalable, VLSI-compatible, and silicon-CMOS


compatible fashion. b, Three-dimensional to-scale rendered schematic
of the RV16X-NANO physical layout (all dimensions are to scale except
for the z axis, which is magnified to clarify each individual vertical
layer). RV16X-NANO leverages a new three-dimensional (3D) physical
architecture in which the CNFETs are physically located in the middle of
the stack, with metal routing both above and below.

Inputs Outputs

LPP>@

XVHV5G
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Inputs Outputs
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UHDG'DWD>@
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Inputs

Outputs

Inputs

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U9DO>@
LPP>@

PHPBZULWHBHQ>@

PHPBDGGU>@
PHPBZULWHBGDWD>@
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^^U9DO``
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/2$' Outputs
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65
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Instruction fetch

Write-back

Register
read

Instruction decode

Execute +
memory
access

PC

Instruction
fetch

Instruction
decode

Register
read

Execute +
memory access

Write-back

ALU

MUX

Decode

Register
le

State

Rotate
load

ADDR

MUX

instr

op

next pc

Single memory port

RD

a

b

Fig. 2 | Architecture and design of RV16X-NANO. a, Block diagram
showing the organization of RV16X-NANO, including the instruction
fetch, instruction decode, register read, execute + memory access, and
write-back stages. See Supplementary Information section ‘RISC-V:


Operational Details’ for definitions of terms. b, Schematics describing the
high-level register transfer level (RTL) description of each stage, including
inputs, outputs and signal connections. Additional information on the
RV16X-NANO is in the Supplementary Information.

596 | NAtUre | VOl 572 | 29 AUGUSt 2019

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