Article reSeArcH
0
0.5
00 .5
D (input node) (Volts)
extract voltage transfer
curve (VTC) parameters
(a)
static noise margin (SNM) (% of VDD)
minimumSNM
(limits pNMS)
0% 25%
101
105
103
occurrences
(# of logi
c stages)
parametervalue
technology node
contacted gate pitch54 nm
gate,contact length 9nm, 9 nm
contact resistance 3
equivalent oxide
thickness (EOT)
0.7 nm
CNT pitch, diameter 2 nm, 1.7 nm
m-CNT resistance 40 k
IOFFtarget 100 nA/μm
layers
gate
source/drain
local interconnect
active region
tech
preferred
corner
p
NM
S pS:
99.999%
99.99%
99.9%
minimum SNM (% of VDD)
0 0.2 0.4
0%
99.9%
99%
90%
(j)
0
0.1
0.2
0.3
0.4
0.5
012
VOH
VIH
VIL
VOL
extracted data
affine model
affine model form:
(k)
EDP-
optimal
design
0.01
0.04
28
energy/cycle
(nJ)
Pareto-
optimal curve
clock frequency (GHz)
parasitic extraction
logic synthesis,
clock tree synthesis,
placement & routing,
parasitic extraction
(sweep over multiple
circuit parameters)
EDP optimization
energy/
cycle
physical designs
extracted netlists
library characterization
material properties
library cell layouts
compact model
0
3
00 .4
experimental
data
compact
model:
VGS VT
= 0.25 V
-VDS(V)
ID
)TNC / Aμ(
library power/timing
clock
frequency
inputs design flow
10
0
interconnect
target clock frequency
select the EDP-
optimal design over
multiple individual
physical designs
EDP optimization
FET/circuit parameters
processor
core:
single
physical
design
CNFET active
regions aligned
s-CNTs
m-CNTs
nand2 nor 2 (b) D flip-flop
MS
clkn
clkb
SS
SH
MH
D
(c) QN(d)
MH
(internal node)
(Volts
)
(VIH, VOL)
(VIL, VOH)
(e)
# m-CNTs in
pull-down network
volt
age
(Volts
)
(f)
where:
r = number of
sampling regions
Mi= number of m-CNTs
in sampling region i
(g)
(h)
(i)
standard
cells:
row 1
standard
cells:
row 2
region with
aligned CNTs
Variable
number of s-CNTs
Variable
number of m-CNTs
regiregion on (^12)
region 3
regiregion on (^45)
region 6
regiregion on (^78)
region 9
regiregion 10on 11
region 12
S1S2
S3
S4S5
S6
S7S8
S9
S10S11
S12
M1M2
M3
M4M5
M6
M7M8
M9
M1M1 (^01)
M1 2
U3 U4 U5
U6
P3,1
N3
,1
P5,1
N5
,1
N6
,1
P6,1
P4,1
N4
,1
P4,2
N4
,2
CLK
Extended Data Fig. 9 | See next page for caption.