siliconchip.com.au Australia’s electronics magazine April 2019 59
the iCEstick into signals which are fed
to the VGA connector, to generate VGA
video. The circuit diagram of this add-
on board is shown in Fig.1.
The horizontal synchronisation
(HSYNC) and vertical synchronisa-
tion (VSYNC) lines are effectively
fed digital pulses via series resistors,
which provide a degree of protection
to the FPGA in case of static electric-
ity and so on.
The red, green and blue VGA signals
are formed by primitive 2-bit DACs,
made using pairs of resistors in a 2:1
ratio, giving four evenly spaced voltage
levels between fully off and fully on.
For example, if pins 3 and 9 of CON1
are held low (0V), then 0V is applied to
pin 2 of CON2, the green signal. If both
these pins are high (3.3V), then pin 2
of CON2 is at 3.3V. If pin 3 of CON1 is
high (3.3V) and pin 9 is low (0V) then
the voltage divider formed by the 560Ω
and 1.1kΩ resistors means that around
2.2V is fed to pin 2 of CON2, while if
those voltages are reversed, pin 2 is at
around 1.1V.
By using various combinations of
levels on the red, green and blue lines,
we can generate 4 x 4 x 4 = 64 differ-
ent colours on the screen.
The 560Ω and 1.1kΩ resistor values
have been chosen to avoid exceeding
the FPGA’s 8mA per pin sink/source
current rating. We found that on some
monitors, this resulted in colours
which were a bit dark, so you may
wish to try slightly lower values (eg,
470 Ω and 910Ω or 430Ω and 820Ω).
If you are unsure, stick with the sug-
gested values.
All timing and signal generation
is done within the FPGA. We won’t
claim the output is fully VGA com-
pliant, but we have had no troubles
using it with a few different monitors
we used for testing.Operating principles
We’re generating a 640x480 pixelVGA signal, which involves scanning
800x525 pixels. The extra pixels are
hidden in black borders outside the
normal display area of the screen (in
the front/back porch and rescan areas).
For a standard 60Hz monitor update
rate, we need a 25.2MHz pixel clock
(800 x 525 x 60Hz).
Our alphanumeric terminal occu-
pies a central 512x384 pixel region
of the 640x480 display image, with
black borders around the edge. We’ve
done this because the 512x384 pixel
region maps to 32x16 alphanumeric
characters, and 32x16 = 512 which is
the number of bytes in each block of
RAM within the FPGA.
It would be possible to combine
multiple RAM blocks to allow a larger
character display (possibly filling the
screen), but that would complicate the
code design somewhat. Making the rel-
evant changes could be a good exercise
for readers who really want to delve
into FPGA programming.1
2
3
4
56
7
8
9
1011
12
13
14
15VSYNCHSYNCRED
GREEN
BLUE1
2
3
4
58710912112 x
68 W1.1kW560 W1.1kW560 W1.1kW
TO iCEstick 560 WCON2VGA OUTPUT
CON1ÓSC 20 1 9 icestick VGA ADAPTOR
61.1kW
560 W
1.1kW
560 W68W68WCON1(under)
to
iCEstick11212 677CON2
VGA
out1.1kW
560 WFig.1: the circuit for ÓSC^20 1 9
our VGA adaptor is
delightfully simple,
since so much of the
hard work is done
by reconfiguring the
blocks inside the FPGA.
Three resistive two-bit DACs are formed
by the 1.1kand 560resistors, to
control the red, green and blue voltage
levels on the VGA connector. The HSYNC
and VSYNC pulses are digital signals
fed straight to the VGA socket, with 68
series resistors for safety. The unusual
pin numbering of CON1 is to match the
numbering on the iCEstick; they are
treated as two side-by-side SIL headers,
even though it’s physically a DIL header.Fig.2: fit the resistors to the PCB
where shown here, then the VGA
socket, which goes on the same side
as the resistors, and finally the 6x2
pin header, on the opposite side.
The resulting assembly then plugs
straight into the iCEstick and a
standard VGA monitor cable.12345678910
1112131415
VGA socket – looking at pins.Here’s the complete (!) project attached to the iCEstick, which in turn
plugs into a free USB socket.