siliconchip.com.au Australia’s electronics magazine April 2019 61
In more detail, when the horizontal
pixel counter is between 0-511, that is
the active part of the display, and the
RGB outputs are driven. The rest of the
time, the RGB outputs remain low, so
the front porch, back porch and bor-
ders are black. When the horizontal
counter is between 592 and 688, pin 7
is set high, creating the HSYNC pulse.
Similarly, the vertical (line) pixel
clock counts from zero to 524, with
the RGB outputs active from 0-383,
and VSYNC is driven high on lines
443-445. The lines between 446 and
524 are the vertical refresh period, so
the RGB outputs remain low.
These sync values have been chosen
by trial and error, to centre the display
on our test monitor.
They can be changed in the FPGA
configuration to adjust the location on
your monitor, although the differenc-
es between the values should remain
the same to maintain the same sync
pulse widths.
Implementing this in the FPGA
We’re using the IceStudio software
to demonstrate what can be done us-
ing this software, and while the IceS-
tudio project looks quite complicated,
it can be broken down into small, easy
to understand functional blocks that
each accomplish one small task.
We hope this gives you an insight
on how easy it is to jump into creating
your own projects with Verilog inside
IceStudio; keep in mind as you work
with FPGAs that the outcome is actu-
ally an arrangement of logic gates and
flip-flops that all work simultaneous-
ly, rather than code that is processed
in sequence.
Screen1 shows the IceStudio pro-
ject in its entirety. The FPGA is con-
figured by connecting various blocks
together, and we’ve labelled groups
of blocks to indicate their purpose.
If you want to examine the design in
more detail as we explain what each
block does, skip to the section below
titled “Installing the software on your
computer”, then come back and read
the following description.
Clock generation is performed by
the area marked PLL in the project
window. The code in this block con-
tains synthesiser directives that de-
scribe how to configure the PLL. The
iCEcube2 software that we reviewed
in our iCEstick tutorial on page 32 is
capable of generating PLL configura-
tion data if you want to experiment
with this block.
To the right of the PLL block and the
left of the HSYNC/VSYNC sections are
the clock dividers.
The small blue block divides the
100.5MHz clock by four to give the
25.125MHz pixel clock, which is then
divided by 800 to give the line clock.
This is in turn divided by 525 to give
the frame clock.
The ACTIVE VIDEO DETECT sec-
tioncompares the pixel and line clocks
to the fixed values indicated above,
producing two outputs which are both
high when the current pixel is part of
the 512x384 pixel active area. These
are fed to the colour decoder, which
generates black unless both (horizontal
and vertical) active video bits are set.
Below ACTIVE VIDEO DETECT is a
section which divides the pixel count
by two to create indexes for the font
ROM. The line count is effectively di-
vided by three, to create the vertical
font index.
But rather than using a divider,
which would be quite large and com-
plex to implement in the FPGA, in-
stead, a separate counter is used,
which is only incremented on every
third pulse from the line clock, thenreset when it reaches 128 (ie, 384 ÷ 3).Serial data handling
The FPGA needs to accept serial
data from the host, both for configu-
ration and to update the displayed
characters and/or colours. The UART
block is shown to the left of the PLL
in Screen1. This is made using open-
source Verilog code that is available
at https://github.com/cyrozap/osdvu,
which also includes a description of
how to interface to it.
We don’t need to send any data back
to the host, so we removed the trans-
mit-specific sections, to save FPGA
resources.
While a microcontroller would wait
and then branch to code to read from
a buffer when the host is sending data
to it, the FPGA is always ready to re-
act, and the data from the UART is
put into the video RAM within nano-
seconds of it arriving, simultaneously
with the video output tasks occurring
elsewhere on the chip.
The UART decoder filters the in-
coming serial data and also holds a vid-Screen3: in the window that appears after clicking View
→ Command Output, the folder containing the generated
Verilog file is visible (highlighted section). Open this folder
and find the file named “main.v”, which is the generated
Verilog equivalent of the IceStudio project.Screen2: if you have successfully built the hardware and
programmed the FPGA, you will be greeted by this display
on your VGA monitor.
Parts list – iCEstick
VGA Terminal
1 Lattice iCEstick FPGA development
board
[Mouser 842-ICE40HX1KSTICKEV,
Digikey 220-2656-ND]
1 double-sided PCB, code 02103191,
49.5 x 32mm
1 2x6 male pin header (CON1)
1 DE-15 (or HD-15) high-density 15-
pin female D-connector (CON2)
[AMP 1-1734530-1,
MULTICOMP SPC15430]Resistors (all 1/4W 1% metal film)
3 1.1kW 3 560W 2 68W