Silicon Chip – July 2019

18 Silicon chip Australia’s electronics magazine siliconchip.com.au

Only N-channel Mosfets seem to be
affected by SEB; P-channel devices ap-
pear to be immune.
Single Event Gate Rupture (SEGR)

• this affects power Mosfets and is
  caused by the breakdown of the oxide
  layer on the Mosfet gate structure. The
  results are similar to an SEB event.

Electrostatic charging of

spacecraft

Spacecraft can acquire an electrical
charge due to their interaction with
charged particles in space.
Generally, spacecraft have a posi-
tive charge on the sunlit side due to
the photoelectric effect, and a nega-
tive charge on the dark side due to
plasma charging.
This charge can occur either on the
surface of or internal to the spacecraft.
This can result in damage to electronic
circuitry and interference with scien-
tific measurements.
Damage can occur due to electric
discharges between adjacent compo-
nents at very different potentials, or

from an electric discharge due to an

accumulated static charge within di-

electric materials due to long-term

bombardment with charged particles.

The satellites most vulnerable to

these effects are in geosynchronous

orbit, where there is a low plasma

density that does not allow a bleed-

off of charge.

Potentials as high as 20kV have

been recorded.

Spacecraft charging avoidance op-

tions are limited, but it can be miti-

gated by having charge dissipating

surfaces, using design practices to

minimise differential charging and

careful consideration of spacecraft or-

bit and space weather during launch

(eg, avoiding solar storms).

Electromagnetic pulses

Apart from nuclear explosions,

electromagnetic pulses (EMP) can

arise from lightning, electrostatic

discharges, switching heavy current

loads, non-nuclear electromagnetic

pulse (NNEMP) weapons and electro-

magnetic forming, as used in industry

to shape certain items.

An EMP can induce strong currents

in materials and damage or destroy

them, wipe magnetic media, interfere

with wireless communications, de-

stroy national power grids and have

many other adverse effects.

Protection against EMP can include

shielding and current limiting devic-

es, but it is difficult to protect an en-

tire power grid.

Recognition of such a risk has lead

to the US “Executive Order on Coor-

dinating National Resilience to Elec-

tromagnetic Pulses” (see siliconchip.

com.au/link/aapz).

See also the report at: siliconchip.

com.au/link/aaq

It is not known if Australia has

any specific plans to deal with such

threats.

Designing to minimise

radiation-induced events

Avoidance or minimisation of ad-

verse events due to radiation can be

achieved through appropriate com-

ponent selection, digital error detec-

tion and correction, use of redundant

components, detection of excessive

current or heat at chip junctions (see

Fig.11) and also shielding.

The problem with shielding is that it

is heavy and is also ineffective against

cosmic rays. It can, however, be effec-

tive against solar flare particles.

Components designed explicitly for

radiation hardness are typically based

on a commercial equivalent, with vari-

ous modifications.

They generally lag behind non-

hardened devices in performance,

partly because of the extra research,

development and certification re-

quired to produce them and also be-

cause some radiation hardening fea-

tures tend to lower performance.

In fact, older, slower devices tend

to tolerate radiation better due to their

larger junctions, so ‘upgrading’ space-

rated components is much more diffi-

cult than their terrestrial counterparts.

In terms of susceptibility to radia-

tion-induced effects, technologies in

order of the least susceptible to the

most susceptible are as follows: CMOS

(silicon on sapphire), CMOS, standard

bipolar, low-power schottky bipolar,

nMOS DRAM (n-type metal oxide

semiconductor dynamic random ac-

cess memory).

Radiation hardening of devices

can be characterised as being based

on physical methods or logical meth-

ods, such as error correction and re-

dundancy.

Physical hardening methods in-

clude:

• fabricating chips on an insulating
  substrate such as sapphire, to re-
  duce the possibility of parasitic
  stray current pathways caused by
  radiation events


• the use of bipolar transistors in inte-
  grated circuits which use two types
  of charge carriers instead of FETs,
  which use just one


• the use of SRAM (static random
  access memory), which is intrinsi-
  cally more radiation-resistant than
  DRAM (dynamic random access
  memory), although it is larger and
  more expensive


• the use of wide band-gap semicon-
  ductors such as gallium nitride and
  silicon carbide instead of silicon,
  which are less likely to be disrupted
  by a given electrical charge injection


• shielding of electronics with mate-
  rials such as aluminium and tung-
  sten, despite the added weight


• shielding of electronics with bo-
  ron-11, which results in less sec-
  ondary emission of radiation when
  struck by primary radiation
  Logical means of radiation harden-
  ing include:


• the use of strong error correct-

Fig.9: the RCA 1802,

one of the first radiation-

hardened CPU chips. Image credit:

CPU collection Konstantin Lanzet, CC

BY-SA 3.0 siliconchip.com.au/link/aapy

Fig.8: the Fairchild Micrologic Type
G three-input NOR gate from 1961,
the first practical integrated circuit,
as used in the Apollo guidance
computer. During its manufacture,
the price dropped from US$1000 to
US$20, leading to its commercial use.
It’s intrinsically radiation-resistant
due to its large size and small
component count (six transistors and
eight resistors). To see how this chip
worked and how it got humanity to
the moon see: siliconchip.com.au/link/
aapx