FEATURE / DEEP DIVE
happen in bursts – you want to perform as
many quick operations on the open row as
possible before having to close it and move
onto the next one.
When the system finishes with a row –
multiple read and write operations can be
performed on it at once – the sense amplifiers
have to write the data back into the cells
(regardless of whether only read operations
have been performed on it), in order to refresh
the row and maintain the existing data.
It’s a highly complex process and, thanks to
its bursty nature, it’s one that means memory
access is very dependent on parallelism, with
multiple memory banks constantly workingin parallel to keep downtime to a minimum
and provide a steady flow of data. This row
and column access also leads us on to one
of the most often misunderstood aspects of
RAM – timings.NO TIME TO DELAY
Around a decade or so ago, one of the hot
new topics of PC enthusiast circles was
the pursuit of low memory timings. All of a
sudden, it wasn’t enough just to have RAM
with a fast clock speed but also RAM with
low timings. But what do those timings
mean, and are they still as important as
they once appeared?Memory timings describe the
performance of a RAM module according
to four parameters, which measure the
time it takes for the memory to respond to
certain internal commands. All four of these
numbers relate back to that whole row/
column layout and row refresh requirement.
The first of the four measurements that
you’ll see slapped on the side of memory
modules is called CAS latency (tCL), or
column address strobe latency. This
figure is generally considered to be the
most important of the four numbers, as it
describes the fastest possible response
time of the DRAM in an ideal scenario.
It’s a measure of how many clock cycles
it takes between a column address arriving
to memory and the data for that address to
start flowing back in response. Crucially, the
desired row must already be active before
this number applies. If it’s not, additional time
is required. The tCL setting is a fixed time
agreed between the memory controller
and the memory, not a minimum as with the
other three numbers.
Next up is tRCD, or row address
to column address delay. This is the
minimum number of clock cycles it takes
to open a row (if a different row isn’t
already open) and access the required
column. In other words, in situations where
a row isn’t already active, it’s the additional
minimum potential delay that’s added
to tCL before data starts being read. So,
the total delay to reading the first bit of
memory from DRAM is now tRCD + tCL.
Next up is row precharge time (tRP),
which is the minimum number of clock
cycles it takes to close the current row
(including precharging the cells from the
currently active row) and open a new
row. This figure again stacks on top of
the previous two measurements, so
the minimum time to read the first bit of
memory if the wrong row is currently
open is tRP + tRCD + tCL.
Finally, we have row active time (tRAS),
which is the minimum number of clock cycles
between a row active command (loading the
row of the array) and issuing the precharge
command (closing the row and precharging
the cells as it leaves). In other words, it’s the
minimum time required for a row to be active
to ensure data can be accessed.You’ll find the memory timings listed
on most memory modules as a row
of four numbersFEATURE / DEEP DIVE
happen in bursts – you want to perform as
many quick operations on the open row as
possible before having to close it and move
onto the next one.
When the system finishes with a row –
multiple read and write operations can be
performed on it at once – the sense amplifiers
have to write the data back into the cells
(regardless of whether only read operations
have been performed on it), in order to refresh
the row and maintain the existing data.
It’s a highly complex process and, thanks to
its bursty nature, it’s one that means memory
access is very dependent on parallelism, with
multiple memory banks constantly workingin parallel to keep downtime to a minimum
and provide a steady flow of data. This row
and column access also leads us on to one
of the most often misunderstood aspects of
RAM – timings.NO TIME TO DELAY
Around a decade or so ago, one of the hot
new topics of PC enthusiast circles was
the pursuit of low memory timings. All of a
sudden, it wasn’t enough just to have RAM
with a fast clock speed but also RAM with
low timings. But what do those timings
mean, and are they still as important as
they once appeared?Memory timings describe the
performance of a RAM module according
to four parameters, which measure the
time it takes for the memory to respond to
certain internal commands. All four of these
numbers relate back to that whole row/
column layout and row refresh requirement.
The first of the four measurements that
you’ll see slapped on the side of memory
modules is called CAS latency (tCL), or
column address strobe latency. This
figure is generally considered to be the
most important of the four numbers, as it
describes the fastest possible response
time of the DRAM in an ideal scenario.
It’s a measure of how many clock cycles
it takes between a column address arriving
to memory and the data for that address to
start flowing back in response. Crucially, the
desired row must already be active before
this number applies. If it’s not, additional time
is required. The tCL setting is a fixed time
agreed between the memory controller
and the memory, not a minimum as with the
other three numbers.
Next up is tRCD, or row address
to column address delay. This is the
minimum number of clock cycles it takes
to open a row (if a different row isn’t
already open) and access the required
column. In other words, in situations where
a row isn’t already active, it’s the additional
minimum potential delay that’s added
to tCL before data starts being read. So,
the total delay to reading the first bit of
memory from DRAM is now tRCD + tCL.
Next up is row precharge time (tRP),
which is the minimum number of clock
cycles it takes to close the current row
(including precharging the cells from the
currently active row) and open a new
row. This figure again stacks on top of
the previous two measurements, so
the minimum time to read the first bit of
memory if the wrong row is currently
open is tRP + tRCD + tCL.
Finally, we have row active time (tRAS),
which is the minimum number of clock cycles
between a row active command (loading the
row of the array) and issuing the precharge
command (closing the row and precharging
the cells as it leaves). In other words, it’s the
minimum time required for a row to be active
to ensure data can be accessed.You’ll find the memory timings listed
on most memory modules as a row
of four numbers