FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

c

uut: ff
Port map (
clk => clk,
D => d,
Q => q);
end Behavioral;

reg.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ff is
Generic( data_width: positive := 1);
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC_vector(data_width - 1 downto 0);
Q : out STD_LOGIC_vector(data_width - 1 downto 0));
end ff;

architecture Behavioral of ff is

begin

process(clk)

begin

if rising_edge(clk) then

q <= d;

end if;

end process;

end Behavioral;

testB_reg.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testB_ff is
Generic( data_width: positive := 4);
end testB_ff;

architecture Behavioral of testB_ff is