FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

d

component ff

Generic( data_width: positive := 1);

Port ( clk : in STD_LOGIC;

D : in STD_LOGIC_vector(data_width - 1 downto 0);

Q : out STD_LOGIC_vector(data_width - 1 downto 0));

end component;

signal clk: std_logic := '0';

signal d: STD_LOGIC_vector(data_width - 1 downto 0) := (others => '0');

signal q: STD_LOGIC_vector(data_width - 1 downto 0) := (others => '0');

begin

process

begin

clk <= '0';

wait for 5us;

clk <= '1';

wait for 5us;

end process;

process

begin

d <= d + '1';

wait for 2.95 us;

end process;

uut: ff

Generic map( data_width => data_width)

Port map (

clk => clk,

D => d,

Q => q);

end Behavioral;

shift_reg.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shift_reg is
Generic(number_of_FF: integer := 16);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;