FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

e

ce : in STD_LOGIC;
rot : in STD_LOGIC;
load : in STD_LOGIC;
load_data : in STD_LOGIC_VECTOR (number_of_FF - 1 downto 0);
data : out STD_LOGIC_VECTOR (number_of_FF - 1 downto 0);
q : out STD_LOGIC);
end shift_reg;

architecture Behavioral of shift_reg is
signal data_buf: std_logic_vector(number_of_FF - 1 downto 0) := (others => '0');
constant all_zeros: std_logic_vector(number_of_FF - 1 downto 0) := (others => '0');
signal q_buf: std_logic := '0';
begin

data <= data_buf;

q <= q_buf;

process(clk)

begin

if rising_edge(clk) then

if rst = '1' then

data_buf <= all_zeros;

elsif load = '1' then

data_buf <= load_data;

elsif ce = '1' then

q_buf <= data_buf(number_of_FF - 1);

data_buf(number_of_FF - 1 downto 1) <= data_buf(number_of_FF - 2 downto 0);

if rot = '0' then

data_buf(0) <= '0';

else

data_buf(0) <= data_buf(number_of_FF - 1);

end if;

end if;

end if;

end process;

end Behavioral;

testB_shift_reg.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity testB_shift_reg is