f-- Port ( );
end testB_shift_reg;
architecture Behavioral of testB_shift_reg is
component shift_reg
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
load : in STD_LOGIC;
rot : in STD_LOGIC;
load_data : in STD_LOGIC_VECTOR (3 downto 0);
data : out STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC := '0';
signal load : STD_LOGIC := '0';
signal load_data : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal data : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal q : STD_LOGIC := '0';signal cnt_test: std_logic_vector(7 downto 0) := (others => '0');
begin
clk_gen: process
begin
clk <= not clk;
wait for 5 ns;
end process;load_data <= "1001";cnt_proc: process(clk)
begin
if rising_edge(clk) then
if cnt_test = x"01" then
load <= '1';
rst <= '0';
cnt_test <= cnt_test + '1';
elsif cnt_test = x"30" then
load <= '0';
rst <= '1';
cnt_test <= cnt_test + '1';
elsif cnt_test < x"50" then
load <= '0';