FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

g

rst <= '0';

cnt_test <= cnt_test + '1';

else

load <= '0';

rst <= '0';

end if;

end if;

end process;

uut: shift_reg

Port Map(

clk => clk,

rst => rst,

rot => ‘0’,

load => load,

load_data => load_data,

data => data,

q => q

);

end Behavioral;

UART_TX.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uart_tx is

generic(

system_clock: integer;

baud_rate: integer);

port (

clk:in std_logic;

tx: out std_logic;

data_send: in std_logic_vector(7 downto 0);

start_send: in std_logic;

done: out std_logic

);

end entity;

architecture beh of uart_tx is

-- Internal Variables