hconstant clk_divider: integer := system_clock / baud_rate;signal tx_clk_cnt: integer range 0 to clk_divider := 0;
signal tx_clk: std_logic := '0';type state_type is (S_wait, S_start, S_b0, S_b1, S_b2, S_b3, S_b4, S_b5, S_b6, S_b7, S_stop);
signal st: state_type := S_wait;signal busy: std_logic := '0';
signal data_buf: std_logic_vector(7 downto 0) := (others => '0');begin
process(clk)
begin
if clk'event and clk = '1' then
if start_send = '1' then
tx_clk_cnt <= 0;
tx_clk <= '0';
elsif tx_clk_cnt = clk_divider then
tx_clk <= '1';
tx_clk_cnt <= 0;end if;
end process;elseend if;tx_clk_cnt <= tx_clk_cnt + 1;
tx_clk <= '0';done <= not busy;process(clk)
begin
if clk'event and clk = '1' then
if start_send = '1' and busy = '0' then
busy <= '1';
data_buf <= data_send;
elsif tx_clk = '1' then
case st is
when S_wait =>
if busy = '1' then
st <= S_start;
end if;
when S_start =>
st <= S_b0;