FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

i

tx <= '0';

when S_b0 =>

tx <= data_buf(0);

st <= S_b1;

when S_b1 =>

tx <= data_buf(1);

st <= S_b2;

when S_b2 =>

tx <= data_buf(2);

st <= S_b3;

when S_b3 =>

tx <= data_buf(3);

st <= S_b4;

when S_b4 =>

tx <= data_buf(4);

st <= S_b5;

when S_b5 =>

tx <= data_buf(5);

st <= S_b6;

when S_b6 =>

tx <= data_buf(6);

st <= S_b7;

when S_b7 =>

tx <= data_buf(7);

st <= S_stop;

when S_stop =>

tx <= '1';

st <= S_wait;

busy <= '0';

end if;
end process;
end architecture;

UART_RX.vhd

end if;

end case;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity uart_rx is
generic (