FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

j

system_clock: integer;
baud_rate: integer
);
port (
RX : in std_logic; -- Receiver input.
DATA : out std_logic_vector(7 downto 0); -- 8 - bits of data received.
done : out std_logic; -- Indicates receiver is currently receiving.
CLK : in std_logic
);
end uart_rx;

architecture beh of uart_rx is
constant divider: integer := system_clock / baud_rate / 2;
signal en_rx: std_logic := '0';
signal cnt_sample: integer := 0; --numără până la 'divider', astfel se determină când trebuie
făcută recepția
signal cnt_bit: integer := 0; --reține bitul recepționat

signal data_rx: std_logic_vector(7 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if en_rx = '0' and rx = '0' then
en_rx <= '1';
done <= '0';
elsif (cnt_bit = 19 and cnt_sample = divider) then
done <= '1';
en_rx <= '0';
else
done <= '0';
end if;
end if;
end process;

process(clk)

begin

if(rising_edge(clk)) then

if(en_rx = '1') then

if(cnt_sample < divider) then

cnt_sample <= cnt_sample + 1;

else

cnt_sample <= 0;

cnt_bit <= cnt_bit + 1;

end if;