else
cnt_sample <= 0;
cnt_bit <= 0;
end if;
end if;
end process;process(clk)
begin
if(rising_edge(clk)) then
if(cnt_bit = 2 and cnt_sample = divider) then
data_rx(0) <= RX;
elsIf(cnt_bit = 4 and cnt_sample = divider) then
data_rx(1) <= RX;
elsIf(cnt_bit = 6 and cnt_sample = divider) then
data_rx(2) <= RX;
elsIf(cnt_bit = 8 and cnt_sample = divider) then
data_rx(3) <= RX;
elsIf(cnt_bit = 10 and cnt_sample = divider) then
data_rx(4) <= RX;
elsIf(cnt_bit = 12 and cnt_sample = divider) then
data_rx(5) <= RX;
elsIf(cnt_bit = 14 and cnt_sample = divider) then
data_rx(6) <= RX;
elsIf(cnt_bit = 16 and cnt_sample = divider) then
data_rx(7) <= RX;
elsIf(cnt_bit = 19 and cnt_sample = divider) then
data <= data_rx;
end if;
end if;
end process;end architecture;
ssd_ctrl.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
entity SSD_CTRL is
Generic(number_of_digits: integer := 4);
Port ( clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR(number_of_digits * 4 - 1 downto 0);
AN : out STD_LOGIC_VECTOR (number_of_digits - 1 downto 0);
k