FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

l

C : out STD_LOGIC_VECTOR (7 downto 0));
end SSD_CTRL;

architecture Behavioral of SSD_CTRL is

constant max_sweeping_value: std_logic_vector(15 downto 0) := x"FFFF";

constant rst_sweeping_value: std_logic_vector(15 downto 0) := x"0000";

signal sweeping_cnt: std_logic_vector(15 downto 0) := (others => '0');

signal digit_select: std_logic_vector(number_of_digits - 1 downto 0) := (0 => '1', others => '0');

signal shift_en: std_logic := '0';

signal ca, cb, cc, cd, ce, cf, cg, dp: std_logic := '0';
begin

dp <= '1';

C <= dp & cg & cf & ce & cd & cc & cb & ca;

process(clk)

begin

if rising_edge(clk) then

an <= not digit_select;

end if;

end process;

sweep_cnt: process(clk)

begin

if rising_edge(clk) then

if sweeping_cnt = max_sweeping_value then

sweeping_cnt <= rst_sweeping_value;

shift_en <= '1';

else

sweeping_cnt <= sweeping_cnt + '1';

shift_en <= '0';

end if;

end if;

end process;

shift_reg: process(clk)

begin

if rising_edge(clk) then

if shift_en = '1' then

digit_select(0) <= digit_select(number_of_digits - 1);

for i in 0 to number_of_digits - 2 loop