FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

m

digit_select(i + 1) <= digit_select(i);
end loop;
end if;
end if;
end process;

digit_display: process(clk)
begin
if rising_edge(clk) then
for i in 0 to number_of_digits - 1 loop
if digit_select(i) = '1' then
if data(i 4 + 3 downto i 4) = x"0" then
ca <= '0';
cb <= '0';
cc <= '0';
cd <= '0';
ce <= '0';
cf <= '0';
cg <= '1';
elsif data(i 4 + 3 downto i 4) = x"1" then
ca <= '1';
cb <= '0';
cc <= '0';
cd <= '1';
ce <= '1';
cf <= '1';
cg <= '1';
elsif data(i 4 + 3 downto i 4) = x"2" then
ca <= '0';
cb <= '0';
cc <= '1';
cd <= '0';
ce <= '0';
cf <= '1';
cg <= '0';
elsif data(i 4 + 3 downto i 4) = x"3" then
ca <= '0';
cb <= '0';
cc <= '0';
cd <= '0';
ce <= '1';
cf <= '1';
cg <= '0';
elsif data(i 4 + 3 downto i 4) = x"4" then
ca <= '1';