FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

q

use IEEE.STD_LOGIC_1164.ALL;

entity testB_sync_vga is
end testB_sync_vga;

architecture Behavioral of testB_sync_vga is
component Sync_VGA
Port ( clk : in STD_LOGIC;
HSync : out STD_LOGIC;
HAddr : out STD_LOGIC_VECTOR (11 downto 0);
VSync : out STD_LOGIC;
VAddr : out STD_LOGIC_VECTOR (11 downto 0);
en_q : out STD_LOGIC);
end component;

signal clk : STD_LOGIC := '0';
signal HSync : STD_LOGIC := '0';
signal HAddr : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
signal VSync : STD_LOGIC := '0';
signal VAddr : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
signal en_q : STD_LOGIC := '0';
begin

clk_gen: process

begin

clk <= not clk;

wait for 7.692 ns;

end process;

uut: Sync_VGA

Port Map(

clk => clk,

HSync => HSync,

HAddr => HAddr,

VSync => VSync,

VAddr => VAddr,

en_q => en_q

);

end Behavioral;

testB_ssd_ctrl.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;