FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

r

use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity testB_SSD_CTRL is
-- Port ( );
end testB_SSD_CTRL;

architecture Behavioral of testB_SSD_CTRL is
component SSD_CTRL is
Generic(number_of_digits: integer := 4);
Port ( clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR(number_of_digits * 4 - 1 downto 0);
AN : out STD_LOGIC_VECTOR (number_of_digits - 1 downto 0);
C : out STD_LOGIC_VECTOR (7 downto 0));
end component;

signal clk : STD_LOGIC := '0';

signal data : STD_LOGIC_VECTOR(15 downto 0) := x"0123";

signal AN : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');

signal C : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');

signal cnt: std_logic_vector(7 downto 0) := (others => '0');
begin

clk_gen: process

begin

clk <= not clk;

wait for 5 ns;

end process;

uut: SSD_CTRL

Port Map(

clk => clk,

data => data,

AN => AN,

C => C

);

process(clk)

begin

if rising_edge(clk) then

cnt <= cnt + '1';

end if;

end process;