FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

cristian i.k_ntxi (Cristian I.K_ntXI) 2023-07-18 10:54:49 UTC #1

cc

"0000000000000000",

"0000000000000000",

"0000111111111000",

"0000100000011000",

"0000000000011000",

"0000000000110000",

"0000000000110000",

"0000000001100000",

"0000000001100000",

"0000000011000000",

"0000000011000000",

"0000000011000000",

"0000000011000000",

"0000000011000000",

"0000000011000000",

"0000000011000000",

"0000000000000000",

"0000000000000000",

"0000111111110000",

"0001100000011000",

"0011000000001100",

"0011000000001100",

"0011000000001100",

"0001100000011000",

"0000111111110000",

"0001100000011000",

"0011000000001100",

"0011000000001100",

"0011000000001100",

"0011000000001100",

"0001100000011000",

"0000111111110000",

"0000000000000000",

"0000000000000000",

"0000111111110000",

"0001100000011000",

"0011000000001100",

"0011000000001100",

"0011000000001100",

"0001100000011100",

"0000111111111100",

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