FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
dd

"0000000000001100",

"0000000000001100",

"0000000000001100",

"0000000000001100",

"0011000000001100",

"0001100000011000",

"0000111111110000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000000000000000",

"0000001100000000",

"0000001100000000",

"0000000000000000",

"0000000000000000"

);

signal dataX: std_logic_vector(15 downto 0):=X"0000";
begin


dataX <= my_rom(conv_integer(address));
process(clk)
begin
data <= dataX;
end process;

end Behavioral;


ROM_extract_pixel.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

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