FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
ee

--caracterul----- 0 1 2 3 4 5 6 7 8 9.
--pozitia-------- 0 1 2 3 4 5 6 7 8 9 10 11


entity ROM_extract_pixel is
Port ( clk : in STD_LOGIC;
adrChar : in STD_LOGIC_VECTOR (4 downto 0);
adrLine : in STD_LOGIC_VECTOR (3 downto 0);
adrCol : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC);
end ROM_extract_pixel;


architecture Behavioral of ROM_extract_pixel is


component ROM_character is
Port ( clk : in STD_LOGIC;
address: in STD_LOGIC_VECTOR (8 downto 0);
data : out STD_LOGIC_VECTOR (15 downto 0));
end component;

signal data: std_logic_vector(15 downto 0):=X"0000";
signal address: std_logic_vector(8 downto 0):= "000000000";
signal x: std_logic_vector(8 downto 0):= "000000000";

begin
U10: ROM_character
Port map(
clk,
address,
data);


WITH adrCol SELECT
q <= data(15) WHEN "0000",
data(14) WHEN "0001",
data(13) WHEN "0010",
data(12) WHEN "0011",
data(11) WHEN "0100",
data(10) WHEN "0101",
data(9) WHEN "0110",
data(8) WHEN "0111",
data(7) WHEN "1000",
data(6) WHEN "1001",
data(5) WHEN "1010",
data(4) WHEN "1011",
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