FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

ff

data(3) WHEN "1100",

data(2) WHEN "1101",

data(1) WHEN "1110",

data(0) WHEN "1111",

'X' WHEN OTHERS;

x(8 downto 4) <= adrChar;

x(3 downto 0) <= adrLine;

address <= x;

end Behavioral;

RAMD.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAMD is
generic (addrWidth : positive := 10;
dataWidth : positive := 8);
Port ( CLKA : in STD_LOGIC;
CLKB : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addrA : in STD_LOGIC_VECTOR (addrWidth - 1 downto 0);
di : in STD_LOGIC_VECTOR(dataWidth - 1 downto 0);
addrB : in STD_LOGIC_VECTOR (addrWidth - 1 downto 0);
do : out STD_LOGIC_VECTOR(dataWidth - 1 downto 0));
end RAMD;

architecture Behavioral of RAMD is
type RAM_type is array(2 ** addrWidth - 1 downto 0) of std_logic_vector(dataWidth - 1
downto 0);
signal RAM: ram_type;
begin

process(clka)

begin

if(clka'event and clka = '1')then

if(ena = '1') then

RAM(conv_integer(unsigned(addra))) <= di;

end if;

end if;

end process;