FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

ii

use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

entity demo is
Port ( CLK100MHZ : in STD_LOGIC;
rst: in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (15 downto 0);
vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
seg: out STD_LOGIC_VECTOR (6 downto 0);
an: out STD_LOGIC_VECTOR (3 downto 0);
RsTx: out STD_LOGIC;
LED: out STD_LOGIC_VECTOR (15 downto 0)
);
end demo;

architecture Behavioral of demo is

component clk_wiz_0 is

Port ( clk_in1 : in STD_LOGIC;

clk_out1: out STD_LOGIC);

end component;

component ROM_extract_pixel is

Port ( clk : in STD_LOGIC;

adrChar : in STD_LOGIC_VECTOR (3 downto 0);

adrLine : in STD_LOGIC_VECTOR (3 downto 0);

adrCol : in STD_LOGIC_VECTOR (3 downto 0);

q : out STD_LOGIC);

end component;

component VGA_pattern is

Port ( clk : in STD_LOGIC;

R : out STD_LOGIC_VECTOR (3 downto 0);

G : out STD_LOGIC_VECTOR (3 downto 0);

B : out STD_LOGIC_VECTOR (3 downto 0);

HAddr : out STD_LOGIC_VECTOR (11 downto 0);

VAddr : out STD_LOGIC_VECTOR (11 downto 0);

HSync : out STD_LOGIC;

VSync : out STD_LOGIC;

en_q : out STD_LOGIC);

end component;

component SSD_CTRL is

Generic(number_of_digits: integer := 4);

Port ( clk : in STD_LOGIC;

data : in STD_LOGIC_VECTOR(number_of_digits * 4 - 1 downto 0);

AN : out STD_LOGIC_VECTOR (number_of_digits - 1 downto 0);