FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
mm

led_ctrl: process(clk65MHz)
begin
if rising_edge(clk65MHz) then
if rst = '1' then
shift_reg_load <= '1';
led_switch_counter <= x"0000_0000";
shift_reg_load_data <= x"8453";
else
if shift_reg_load = '1' then
shift_reg_load <= '0';
end if;
if led_switch_counter < x"03DF_D23F" then
led_switch_counter <= ssd_display_counter + '1';
shift_reg_ce <= '0';
else
led_switch_counter <= x"0000_0000";
shift_reg_ce <= '1';
end if;
end if;
end if;
end process;

shift_r: shift_reg
Port Map(
clk => clk65MHz,
rst => rst,
ce => shift_reg_ce,
rot => '1',
load => shift_reg_load,
load_data => shift_reg_load_data,
data => shift_reg_q);

-- trimite "Hello world" pe UART
char_sweep: process(clk65MHz)
begin
if rising_edge(clk65MHz) then
if uart_tx_done = '1' and uart_tx_done_prev = '0' then
uart_data_send <=
std_logic_vector(to_unsigned(natural(character'pos(uart_data_array(char_counter))), 8));
uart_start_send <= '1';
uart_tx_done_prev <= '1';
if char_counter = uart_data_array'length - 1 then
char_counter <= 0;
else
char_counter <= char_counter + 1;
end if;
else
uart_start_send <= '0';
uart_tx_done_prev <= '0';
end if;
end if;

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