FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

tt

function add_f (A,B: data_type) return data_type is

variable m: data_type;

begin

m:=a + b;

return m;

end add_f;

procedure sub_p (signal A: in data_type; signal B: in data_type; signal Q: out data_type) is
begin
Q <= A - B;
end sub_p;
end package body;

testB_pkg_demo.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity testB_pkg_demo is
end testB_pkg_demo;

architecture Behavioral of testB_pkg_demo is
component pkg_demo
Port ( CLK100MHZ : in STD_LOGIC;
rst: in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (15 downto 0);
LED: out STD_LOGIC_VECTOR (15 downto 0)
);
end component;

signal clk : STD_LOGIC := '0';

signal a, b, q_add_f, q_sub_p: std_logic_vector(2 downto 0) := (others => '0');

signal demo_input: std_logic_vector(15 downto 0) := (others => '0');

signal demo_output: std_logic_vector(15 downto 0) := (others => '0');

signal cnt_test: std_logic_vector(7 downto 0) := (others => '0');
signal rst: std_logic := '0';
begin

clk_gen: process

begin

clk <= not clk;

wait for 5 ns;

end process;

demo_input(15 downto 13) <= a;

demo_input(12 downto 10) <= b;

q_add_f <= demo_output(2 downto 0);

q_sub_p <= demo_output(5 downto 3);