FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
uu

cnt_pgoc: process(clk)
begin
if rising_edge(clk) then
if cnt_test = x"01" then
a <= "010" after 1ns;
b <= "011" after 1ns;
cnt_test <= cnt_test + '1' after 1ns;
elsif cnt_test = x"05" then
a <= "011" after 1ns;
b <= "001" after 1ns;
cnt_test <= cnt_test + '1' after 1ns;
elsif cnt_test = x"09" then
rst <= '1' after 1ns;
cnt_test <= cnt_test + '1' after 1ns;
elsif cnt_test < x"10" then
rst <= '0' after 1ns;
a <= "101" after 1ns;
b <= "100" after 1ns;
cnt_test <= cnt_test + '1' after 1ns;
else
a <= "000" after 1ns;
b <= "000" after 1ns;
end if;
end if;
end process;

uut: pkg_demo
Port Map( CLK100MHZ => clk,
rst => rst,
sw => demo_input,
LED => demo_output
);
end Behavioral;

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