FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

(Cristian I.K_ntXI) #1
54

"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",
"0000000000000000",

"0000000000000000",
"0000011111100000",
"0000110000110000",
"0001110000111000",
"0011100000011100",
"0011000000001100",
"0011000000001100",
"0011000000001100",
"0011000000001100",
"0011000000001100",
"0011000000001100",
"0011100000011100",
"0001110000111000",
"0000110000110000",
"0000011111100000",
"0000000000000000",

"0000000000000000",
"0000000110000000",
"0000001110000000",
"0000011110000000",
"0000110110000000",
"0001100110000000",
"0000000110000000",
"0000000110000000",
"0000000110000000",
"0000000110000000",
"0000000110000000",
"0000000110000000",
"0000000110000000",
"0000000110000000",
"0001111111111000",
"0000000000000000"
);

begin


signal dataX: STD_LOGIC_VECTOR (15 downto 0):=X" 0000 ";

dataX <= my_rom(conv_integer(address));
process(clk)
begin
data <= dataX;
end process;
end Behavioral;

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