Design_World_-_Internet_of_Things_Handbook_April_2020

36 DESIGN WORLD — EE NETWORK^4 •^2020 eeworldonline.com | designworldonline.com

A detailed analysis of the OTA updates

will help determine the most appropriate

memory bill-of-material.

In recent years, BLE SoCs have

signifi cantly reduced their total active

current consumption while maintaining a

low deep-sleep current. The reason is the

migration of silicon technology from larger

geometries (0.18 μm, 90 nm and 65 nm) to

much more optimized technology nodes

(55 nm and 40 nm). Use of 40-nm geometry

combined with the integration of an on-chip

dc-dc converter has tremendously reduced

the overall current consumption of the

EFR32BG22 SoC.

For example, the Arm Cortex-M33

CPU requires 54 μA/MHz when running

Coremark from the on-chip fl ash when the

on-chip dc-dc converter is disabled. The

same operation only requires 37 μA/MHz

when the same dc-dc converter is activated.

In deep-sleep mode, the RAM

retention is critical, both because it can

represent a signifi cant portion of the power

budget and because RAM retention will

allow a faster boot when the BLE SoC

must return to active mode. From a design

perspective, the use of low-leakage SRAM

blocks has enabled silicon designers to

keep the deep-sleep current

in the range of 1μA. An

additional key consideration

when selecting a BLE SoC is

the size of each SRAM block

that can vary. The ability to

select the size of the RAM to

be retained will help minimize

power consumption in deep-

sleep mode. The EFR32BG22

SoC integrates independently

selectable SRAM blocks for a total of 32 kB

of on-chip RAM.

Finally, the combination of clock gating

and power gating techniques allow the

BLE SoC to completely shut down certain

portions of the device depending on its

mode of operation. The activation of these

features is automatic, and their details are

almost invisible to application developers.

SOFTWARE ENABLEMENT

Minimizing power consumption in BLE

applications requires highly optimized

scheduling of radio activity, maximizing the

time spent in the lowest possible energy

mode while maintaining the precise timing

the protocol requires. To accurately control

transmitted power, the BLE stack integrates

the confi guration of the dc-dc converter. The

stack comes via a software development

kit (SDK), which is fully integrated with

an integrated development environment

(IDE). The IDE includes a network analyzer

that captures data directly from the SoC

radio. An advanced energy monitor also

correlates power consumption to code

location. A visual GATT confi gurator is

included to enable implementation of

standard Bluetooth SIG profi les or custom

services. These tools allow development of

BLE applications that are fully integrated with

the hardware design, allowing developers

to focus on higher level design choices that

affect power consumption. Also integrated

into the SDK is secure bootloader support

for fi rmware updates, both OTA and through

a serial interface.

IoTMark-BLE active profi le

BLE

Server -

DUT

BLE

Client -

Radio

Manager

O/S 12C LPF notifyBLE 12C LPF

BLE

write

Queue

Queue Queue

Queue

BLE

write

BLE

CRC notify

Verify Verify

CRC

O/S

PhyLink

PhyLink

Application wakeup interval

Application wakeup interval

BLE connection interval

Tx Tx

Rx Rx

Rx Rx

Tx Tx

The IoTMark-BLE benchmark profi le developed

by the Embedded Microprocessor Benchmark

Consortium can help assess power consumption.

It spells out a communications path between an

emulated sensor, the edge node processor and an

emulated gateway. The benchmark measures the

energy required to power the edge node platform

and to run the tests fed by the benchmark.

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