Extended Data Fig. 1 | Device fabrication and magnetic characterization.
a, Schematics of main nanofabrication processes for magnetic DW logic
circuits. (i) Ion milling of magnetic Pt/Co/Al multilayer to create magnetic
strips, (ii) ion milling to produce magnetic racetracks and logic gates, and
(iii) oxidization of the Al layer in the OOP regions. The inset shows an SEM image
of the 50-nm-wide PMMA mask used to protect the IP region of the NAND gate
shown in Fig. 3a during oxygen plasma treatment. The scale bar is 100 nm.
b, Polar MOKE measurement of the IP and OOP regions on application of an
OOP magnetic field. c, Anomalous Hall measurement of the OOP region on
application of an IP magnetic field.