Extended Data Fig. 5 | Various cascaded DW logic circuits. a, AND gate
fabricated by cascading one NAND gate and one NOT gate. b, Cascaded DW
logic circuit with a NAND gate and a NOR gate. Green and purple in the
schematic correspond to ⊙ and ⊗ magnetization, respectively. There is an
inverter placed in the bias reservoir of the NOR gate highlighted with the green
box, giving a bias of ‘1’, as shown in inset, whereas the bias for the NAND gate
is ‘0’. c, Two-bit multiplexer constructed by cascading three NAND gates and
one NOT gate. d, Half-subtractor constructed by cascading four NAND gates
and one NOT gate. e, Extensive cascaded DW logic circuits including 10 NAND
gates and 11 NOT gates. The bright and dark areas in the device regions in the
MFM images correspond to ⊙ and ⊗ magnetization, respectively. The MFM
images are captured after saturation with an OOP magnetic field to set the
initial magnetization direction to ⊙ in all of the reservoirs, followed by current
pulses to obtain the final states. All the scale bars are 500 nm.