Fig.2: block diagram of the ADF4351 wideband synthesiser IC. The integrated voltage-controlled oscillator has an output
frequency range of 2.2 to 4.4GHz, which, when combined with the RF divider, provides the ~35MHz to 4.4GHz range. The
fractional-N PLL controls the frequency from its three registers via the equation: FOUT = FFB× (INT + FRAC ÷ MOD).
The bottom view of
this module is shown
at approximately
twice actual size. The
bottom of the board is
populated by fi ve 10kΩ
pull-down resistors
for the breakout pin
connections.by the dual varicap diode shown to its
right, using a tuning voltage fed in via
the VTUNE pin.
Above the VCO core, you can see the
phase comparator and charge pump,
both blue. The charge pump output
goes to the CPOUT pin, so that an ex-
ternal low-pass fi lter can be used to
smooth the pulsating output of the
charge pump before it is fed back into
the ADF4351 via the VTUNE pin.
The differential outputs from the
bottom of the VCO core go to three dif-
ferent destinations. One of these is to
the yellow ‘RF DIVIDER’ block to its
right. This programmable frequency
divider can divide the VCO output
frequency by 1 (ie, no division), 2, 4,
8, 16, 32 or 64.
This lets the chip generate low out-
put frequencies while the VCO core is
operating at much higher frequencies
(2.2-4.4GHz).
The outputs from the RF divider are
fed directly to the chip’s main RF out-
put stage, which drives the A+ out and
A– out pins. The RF divider outputs
also go to the inputs of two different
multiplexers (digital selector switch-
es), shown in mauve.
The auxiliary multiplexer on the
right switches between the direct out-
put lines from the VCO core and the
outputs from the RF divider and so
determines which is fed to the auxil-
iary RF output stage and then to the
B+ and B– output pins. The PDBRF
pin allows both RF output stages to be
disabled when they are not needed, to
save power.
The feedback (F/B) multiplexer at
left determines which of the same two
signal pairs go to the feedback divider,
in the yellow box. It’s also rather more
complex than the simple feedback di-
vider shown in Fig.1. That’s because
the ADF4351 offers the ability to im-
plement either an integer-N or a frac-
tional-N PLL, as required.
So the feedback divider needs three
registers which hold the integer divi-
sion value, the fractional division value
and the modulus value, plus control
circuitry labelled ‘third-order fractional
interpolator’. This circuitry effectively
allows the feedback frequency to be di-
vided by a rational number (fraction).
The output of this divider is then fed,
via a buffer, to the phase comparator.
The circuitry shown in the upper-
left corner of Fig.2 takes the input
from the external reference oscillator
(fed into the REFIN pin) and processes
it before feeding it to the other phase
comparator input.
As mentioned earlier, one of the re-
fi nements to earlier PLLs was to add areference signal frequency divider, so
that high-frequency reference oscilla-
tors could be used; hence the 10-bit
R counter.
But the ADF4351 also provides a
frequency doubler and an additional
divide-by-two stage for the reference
input, both of which can be switched
in or out under software control. This
gives the chip a great deal of fl exibility.
The whole chip is controlled by
means of a simple 3-wire serial periph-
eral interface (SPI), shown at centre
left of Fig.2.
Serial data from the PC or micro-
controller is fed in via the DATA pin,
clocked into the serial data register and
function latch via clock pulses fed to
the CLK pin, and then latched into the
various control registers by feeding in
a pulse via the LE (latch enable) pin.
All functions of the ADF4351 chip
are confi gured using six 32-bit control
words, sent over this serial bus.
Multiplexer C and the other blocks at
the upper right of Fig.2 allow external
monitoring of the ADF4351’s status.