Practical_Electronics-May_2019

for the gate pulse at which the com-
parator switches state. When the gate
pulse voltage exceeds 2V, the compara-
tor U702.1 output will rapidly go from
a negative to a positive voltage. This
positive-going voltage via D704 cre-
ates a short duration pulse at pin 1 of
U701.1. The pulse width is determined
by the values of the RC circuit of C705
and R705. U701.1 and U701.2 form a
fl ip-fl op or latch circuit, with pin 1
being the set and pin 6 the reset. The
pulse at pin one sets the fl ip-fl op so its
output at pin 4 of U701.2 – point ‘A1’

• goes high, which turns off bilateral
  switch U705.3 and turns on bilateral
  switch U705.2. C715 (and C718 if range
  switch is set to ‘long’) begins to charge
  up at a rate depending on the Attack
  pot (VR701). The voltage across C715
  is buffered by U704.2 and connects to
  the ADSR1 output bus through R719.
  So, we are now in the attack phase
  with the period set by the RC circuit
  of VR701 + R720 and C715 (+C718).
  The ADSR output voltage also feeds
  a comparator (U704.3) with its thresh-
  old set to 10V by U704.4, R716 and
  R718. When the attack voltage ex-
  ceeds 10V, the output of U704.3, pin
  8, quickly goes from a negative state
  to a positive state. This positive-go-
  ing signal resets (pin 6) the fl ip-fl op
  of U701.1 and U701.2 with its output
  (pin 4) point ‘A1’ going low. As the
  gate signal is still present at pin 13 of
  U701.4 via Schmitt inverters U703.1
  and U703.6, point ‘R1’ remains low,

but with point ‘A1’

going low, bilateral

switch U705.2 opens.

These conditions also

cause U701.3 output,

pin 10 (point ‘D1’)

to go high indicating

that we are now in the

decay phase.

With point ‘D1’ high,

bilateral switch U705.1

closes, which discharg-

es C715 (plus C718)

through the decay pot

(VR702 plus R720).

This time, C715 (plus

C718) will only dis-

charge to the voltage level at the output

of U704.1, which is the sustain level set

by VR703. This is now a steady-state

condition and will remain so until the

gate pulse is removed, at which point

C715 (plus C718) is discharged to

ground when bilateral switch U705.3

closes through the release pot (VR704

plus R720).

If the gate is applied and release

before the decay phase, the output

of U703.1 goes high and resets the

fl ip-fl op, so that the release phase is

immediately commenced.

If the mode is changed to trigger at

S703, a trigger pulse is generated with

U702.2 and the fl ip-fl op latches as in

the gate mode. However, on completion

of the attack phase and as there is no

gate signal present, the release phase

is executed. Therefore, in trigger mode

the ADSR is actually an AR envelope

generator with the period independent

of how long a key is present.

Repeat gate circuit description

The repeat gate generator in Fig.65 is

a square wave oscillator used to con-

tinually trigger the ADSR envelope

generators, especially in trigger mode.

U5 has positive feedback applied

through R41 to its non-inverting input.

On power up, U5’s output may be

high or low as it is indeterminate, but

let’s assume low at around –11V. C22,

which is a non-polarised aluminium

capacitor and was at ground potential

begins to charge towards –11V through

VR12 plus R38. A potential divider

of R41 and R40 hold the non-invert-

ing input at around –1.4V. Eventually,

C22 charges up a voltage lower than

–1.4V and as U5 acts as a comparator,

its output fl ips high to +11V. Now the

voltage at the non-inverting input is

held at +1.4V and C22 begins to charge

towards +11V. Once the voltage across

C22 exceeds +1.4V, U5 fl ips low again

and the cycle repeats – oscillates. LED

D4 driven by Q4 indicates the state of

the pulse output.

Sample and Hold (S&H) circuit

description

The S&H circuit of Fig.67 consists of

two sections, the sample and hold plus

a pulse generator. The pulse generator is

very similar to the repeat gate generator

described above. The main difference

is the introduction of D1, which quick-

ly charges C17 through R24 when U3

output is high, bypassing the sample

rate pot (VR9). Unlike the square wave

output from the repeat gate generator,

the S&H clock is a pulse waveform with

a short positive-going pulse with a fre-

quency range of around 0.5 to 50Hz.

The S&H section has a choice of two

input signals to sample, LFO2 output

and the white noise source, selected by

S1. The selected input signal is applied

to the input level pot (VR11) and from

there to the inverting input of op amp

U4.1 via R27. U4.1 inverts this signal

with a gain of 0.5 and offsets the volt-

age to a level of about 6.5 to 7V. The

output of U4.1 is applied to the sam-

pling FET transistor switch (Q2). Q2

provides a higher off resistance when

the signal on the source pin ‘S’ is kept

above ground potential.

The pulse output from the clock gen-

erator is applied via the differentiator

circuit of C11 and bias network of R22

and R23 to the gate pin of Q2 to shorten

Fig.64. ADSR1 and ADSR2 assembled.
(Whoops, I managed to solder the IC
socket for U804 upside down!)

Fig.66. Repeat gate assembled.

Fig.65. MIDI Ultimate repeat gate circuit.