Semiconductor Fundamentals Unit 6 – Transistor Load Lines and Gain
Exercise 1 – Base-Emitter Bias Potentials
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to demonstrate the relationship
between the transistor base-emitter voltage and the base current by using a transistor circuit. You
will verify your results with a multimeter.
DISCUSSION
- Forward bias and reverse bias dc conditions of the transistor base-emitter junction are similar
to those of a diode PN junction. - Silicon transistors have a forward voltage drop between 0.5 Vdc and 0.75 Vdc. Germanium
transistors have forward voltage drops between 0.15 Vdc and 0.3 Vdc. - Once forward voltage has been reached, forward current begins to flow and increases very
rapidly with small increases in forward voltage. - Most transistor base-emitter junctions can not tolerate reverse voltages greater than 5 Vdc to
6 Vdc. - Transistor base-collector junctions, which are normally reverse biased, can tolerate reverse
voltages of in the range of 60 Vdc to 75 Vdc. This maximum reverse bias voltage is
documented in the transistor specification sheet and is referred to as the breakdown voltage. - Exceeding the breakdown voltage will damage the transistor.
- When the base-emitter junction is forward biased and base current flows through the
junction, current also flows through the base-collector junction regardless of its bias. - A transistor with a forward biased base-emitter junction and a reverse biased base-collector
junction is operating in the linear region. - A transistor in saturation has maximum current flow through the collector.
- This exercise will demonstrate the relationship between the base-emitter voltage drop and the
base current with the collector open. - Subscript BEO represents Base-Emitter with the collector terminal Open.