Digital Logic Fundamentals Unit 5 – Flip-Flops
When a flip-flop is set or preset, the Q output is put in a high (logic 1) state.
Reset or clear puts the Q output in a low (logic 0) state.
Some flip-flops have inputs for a clock signal. A specific logic level (level-triggered) or a
transition (edge-triggered) of the clock signal enables the flip-flop to respond to the logic level
of the data signal.
Two types of clock signals that activate flip-flops are shown. A symbol at the clock (CLK) input
identifies the clock signal.
The positive transition (edge) of the clock enables the flip-flop on the left to respond to the data
input. The CLK symbol is a triangle.
The negative transition (edge) of the clock enables the flip-flop on the right to respond to the
data input. A circle and a triangle represent the CLK symbol.