Digital Logic Fundamentals Unit 5 – Flip-Flops
Exercise 2 – D-Type Flip-Flop
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to determine the characteristics of a D-
type flip-flop by observing the logic states of the outputs in response to the input signals. You
will verify your results with an oscilloscope.
EXERCISE DISCUSSION
- The schematic symbol shows a typical D-type flip-flop. There is one data input (D) and a
clock input (CLK). - A PR (preset) input sets the flip-flop and a CLR (clear) input resets the flip-flop.
• The two outputs, Q and Q, are complementary.
- A low (logic 0) at PR sets Q high (logic 1).
- A low at CLR resets Q low.
- If either the PR or CLR inputs remain in a low state, the flip-flop is locked in its set or reset
state, respectively; data or clock signals have no effect on Q and Q.
- A low (logic 0) at PR sets Q high (logic 1).
- The small circle and triangle at the CLK input indicate that the negative edge of the clock
signal activates the data (D) input. - The data input must be stable before and after the flip-flop is clocked.
- The logic state of the data is input to the D-type flip-flop only during the transition of the
clock signal from high to low. - This is a timing diagram showing the relationship between the data input (D), the outputs (Q
and Q), and the clock signal (CLK).
• Q equals the D input after the negative edge of the CLK. Q is the complement of D and Q.
• Once a D-type flip-flop is clocked, changes to the logic state of D do not affect Q and Q
until there is another negative edge of the CLK signal.- The Q output is logic 1. If input D is logic 0 during the next negative edge of the clock
signal, the Q output changes to logic 0. - For example, if PR is logic 1 and CLR is logic 0, the D-type flip-flop is reset: Q is logic 0