Digital Logic Fundamentals Unit 8 – TTL and CMOS Comparison
Exercise 1 – Trigger Levels of TTL and CMOS Gates
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to demonstrate the input voltage at
which the output of a TTL gate or a CMOS gate changes logic states by using the TTL/CMOS
COMPARISON circuit block. You will verify your results with an oscilloscope and a
multimeter.
EXERCISE DISCUSSION
- TTL uses 5 Vdc and ground as the supply voltage.
- The CMOS supply voltage is 5,10, or 15 Vdc.
- The CMOS input and output levels are between the supply voltages (VDD and VSS).
- At some voltage between VIL and VIH the gate output changes states.
- TTL levels are: VIL= 0.8 Vdc and VIH = 2.0 Vdc.
- CMOS levels are: VIL = 1.0 Vdc and VIH = 4.0 Vdc.
- CMOS has a better noise margin than TTL.
- CMOS is low power at low frequencies.
- CMOS power increases with frequency.
- Open collector TTL gates can generate CMOS logic levels when a resistor is used to pull the
output to VDD.