The 8051 Microcontroller and Embedded

Department of Computer Scien

ce and Information Engineering

National Cheng Kung University, TAIWAN

HANEL

EXTERNAL HARDWARE INTERRUPTS Edge-Triggered Interrupt(cont’)

D7

D0 IT0

IE0

IT1

IE1

TR0

TF0

TR1

TCON (Timer/Counter) Register (Bit-addressable)TF1

Timer 0 overflow flag. Set by hardware when timer/counter 0 overflows. Cleared by hardware as the processor vectors to the interrupt service routine

TCON.5

TF0

Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 on/off

TCON.4

TR0

Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 on/off

TCON.6

TR1

Timer 1 overflow flag. Set by hardware when timer/counter 1 overflows. Cleared by hardware as the processor vectors to the interrupt service routine

TCON.7

TF1