SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

272 CHAPTER 6. BIPOLAR JUNCTION TRANSISTORS

FET

BJT

Fmin

1+b-1/2

1

f

Figure 6.14: Minimum noise figure versus frequency for a BJT.

RL

n

A

B

C D

RL

RL RL

Io

Io

Ib

Figure 6.15: One gate drivingngates in a CML circuit.

Typically,β∼ 50 is desirable in such applications.

Flash analog-to-digital converters

An m-bit flash ADC is shown in figure 6.16 to illustrate the need for highβ’s in comparators
using BJT-based differential amplifiers. These architectures are based on usingN=2mresistors
in a reference ladder connected to a reference voltageVrefand comparing each node voltage to
the input voltageVin. If the input voltage is betweenVjandVj+1, the comparatorsA 1 through
Ajwill produce a 1 at their output, and the rest will produce a zero. This output is connected via
a decoder to a digital output. It is imperative that the voltage at any node, sayVj, be a predictable