SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

6.5. BJT DESIGN LIMITATIONS: NEED FOR BAND TAILORING 273

IB

A 1

A 2

IB

IB

Aj

Aj+1

IB

IB

VRef Vin

AN

Decoder

Digital

Output

Rμ

Rμ

Rμ

Rμ

Rμ

Vj

Vj+1

V 1

V 2

VN

2 m comparators

Figure 6.16: Circuit diagram of an m-bit flash analog-to-digital converter,N=2m.

function of the number of resistors, i.e.

Vj=

(j−1)

N

Vref

However, the base current flowing into the comparators causes a deviation from this linear be-
havior. It is clear that the nodes 1 andNhave minimum deviation, since they are proximal to
the voltage supplies. However, as the nodes progress away from 1 andNtoward the center of
the array, the deviation increases because of a continuously increasing fraction of base current
IBdrawn by the comparators. The maximum deviation is thus instinctively understood to be at
the center nodej=N/ 2 and is

〈ΔV〉=

1

8

N^2 RuIB (6.5.30)

ThereforeIBshould be reduced as much as possible, and henceβshould be maximized.β>
100 is desirable for such applications.