SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

478 CHAPTER 9. FIELD EFFECT TRANSISTORS: MOSFET

geometrical analysis gives

Q′B

QB

=1−

dj

L

[√

1+

2 dB

dj

− 1

]

AsLincreases,Q′B/QB→ 1 approaching the long channel case as expected. AsdB/djbe-
comes small (the case for largedj) which is shown in figure 9.29 then

Q′B

QB

=1−

dB

L

In general
Q′B
QB

− 1 −

β 1 dB

L

this leads to
ΔVT=2β 1

s

ox

tox

L

(2φF+VBS)

whenVBSis the substrate bias andβ 1 is a parameter based on specific geometry.
Hot Electron Effects
As the channel lengths shrink, the electric fields in the channel increase if the supply voltages
are kept fixed. The carriers become very “hot,” i.e., they acquire higher kinetic energies than the
thermal energy in such devices. These hot electrons can be injected into the oxide barrier causing
a tunneling gate current. They can also cause deterioration of the device by breaking bonds in
the semiconductor-oxide interface region or causing oxide charging. This damage is especially
dangerous since over a period of time the device degrades and eventually the circuit based on the
device loses its functionality. High fields also cause impact ionization near the drain end of the
channel. To avoid hot electron devices, MOSFETs are being designed so that the electric field
does not become very large in any region of the device.

9.6.4 Parasitic Bipolar Transistors and Latch-up in CMOS ...........

CMOS circuits, while having the important benefit of low power consumption, have an im-
portant undesired property. This effect, known as latch-up, results from the presence of parasitic
bipolar transistors present in integrated circuits. In figure 9.31 we show the origins of the para-
sitic bipolar transistors in a CMOS structure. We can see that in the CMOS structure there is an
npnbipolar transistor and apnptransistor in close proximity. As can be seen, thenpnandpnp
transistors form a positive feedback circuit. The resistancesR 1 ,R 2 ,R 3 ,andR 4 are parasitic
resistances associated with then-substrate andp-well regions, as shown.
If we examine the two-terminal current betweenAandBas a function of bias, we find that up
to a certain bias,VL, the current is very low (∼μA range). However, above this critical voltage
VL(related to the punch through of the transistor, typically∼ 10 V), the two transistors start to
conduct and the current rises abruptly to the level of milliamperes. The current is now controlled
by the resistorsR 3 andR 4. This phenomenon is calledlatch-up. Latch-up can occur whenever
the voltages applied to input or output cause forward biasing ofpnjunctions in the devices and