SEMICONDUCTOR DEVICE PHYSICS AND DESIGN

480 CHAPTER 9. FIELD EFFECT TRANSISTORS: MOSFET

p+ p+ n+

R 2

R 3

R 1

R 4

n substrate pnp

p+ n+ n+

npn

p well

DS

I

+ V

SD

–

(a)

Slope =^1

R 3 ||R 4

VL

VOLTAGE, V

C

URRENT

,

I

(b)

A B

Figure 9.31: (a) a schematic of the parasitic effects that lead to CMOS latch-up problems. (b)
current versus voltage effect. the onset of latch-up is represented by a sharp rise in the parasitic
current.

can cause permanent damage to the chips. To avoid latch-up it is important that device design be
such that the bipolar transistor gain is low.

9.7 SUMMARY.....................................

In this chapter we have discussed the basic operating principles of one of the most important
devices in solid state electronics. The MOS capacitor and the MOSFET are key devices in almost