Inside RS-485One way to ensure that a driver is disabled by the end of the Stop bit is to derive
the driver-enable signal from the data. The driver-enable signal can go low to
disable the driver during every Stop bit, logic-1 data bit, and whenever the
driver is idle (isn’t transmitting a word). The driver-enable signal can go high to
enable the driver during every Start bit and logic-0 data bit. Figure 6-14’s cir-
cuit uses this approach. An added benefit of the circuit is reduced power con-
sumption. No drivers are enabled when the line is idle and a driver is enabled
for only an average of half the time required to transmit a word.
At RS-485 transceiver SN75176B, when the data input at pin 4 goes low (logic
0), the driver-enable input (DE) at pin 3 goes high, enabling the driver and
causing the differential data on pins 6 and 7 to follow pin 4. When pin 4 goes
high (logic 1), pin 6 of Schmitt-trigger inverter 74AC14 goes high. The
0.001μF capacitor charges through the 27k and 390Ω resistors. After a short
delay, pin 9 of the 74AC14 goes high and DE goes low. DE thus remains high
while the line switches to logic 1 and for a short time afterwards.
After the delay, pin 3 on the SN75176B goes low, disabling the driver. The data
on pins 6 and 7 follows pin 4 as it switches state and remains at a logic 1 after
the driver is disabled (Figure 6-15). When the data input goes low again, DE
follows, going high to enable the driver.
With the components shown, the delay in switching the driver off is approxi-
mately 27 μs. Ideally, the delay is half of one bit width. In reality, the computersFigure 6-15: A transceiver’s driver-enable signal (bottom) can be derived from the
transmitted data (top).